1. Field of the Invention
The present invention relates generally to a semiconductor device. More particularly, the present invention relates to a trench isolation structure and a method of forming the same.
2. Description of the Related Art
As the size of a semiconductor device becomes smaller, an aspect ratio of a trench intended for device isolation increases. A trench having a high aspect ratio may be filled with multiple layers of materials.
Disadvantages of forming a conventional trench isolation layer are described below with reference to FIGS. 1 and 2.
Referring to FIG. 1, a trench mask pattern 20 is formed on a semiconductor substrate 10. Using the trench mask pattern 20 as an etching mask, the substrate 10 is anisotropically etched to form a trench 30. During the formation of the trench 30, the substrate 10 is subjected to damage. In order to remove this etching damaged region, a wall of the trench 30 is subjected to a thermal oxidation process to form an oxide layer 40.
A lower device isolation layer of polysilicon or spin-on-glass (SOG) is formed on an entire surface of the semiconductor substrate including the thermal oxide layer 40. The lower device isolation layer is etched so that a top surface of the lower device isolation layer is at a lower level than a top surface of the substrate 10. As a result, a lower isolation pattern 50 is formed to fill a lower portion of the trench 30. An upper device isolation layer 60 formed of high density plasma (HDP) oxide or undoped silicate glass (USG) is formed on an entire surface of the semiconductor substrate including the lower isolation pattern 50.
A very high aspect ratio prevents an HDP oxide film or a USG film from filling the trench 30, therefore, it is necessary to reduce the aspect ratio of the trench 30. The lower isolation pattern is intended for this purpose. The lower isolation pattern 50 is preferably made of a material with better filling characteristics, such as polysilicon or SOG. Thus, the aspect ratio of the trench 30 is reduced by the lower isolation pattern 50, thereby enabling the upper device isolation layer 60 to fill the upper portion of the trench 30.
Referring now to FIG. 2, the trench mask pattern 20 is exposed by etching the upper device isolation layer 60 to form an upper isolation pattern 61. The exposed trench mask pattern 20 is then removed to expose the top surface of the semiconductor substrate 10. Next, a thermal oxidation process is carried out to form a gate oxide layer 70 on the exposed top surface of the substrate 10.
If the lower isolation pattern 50 is made of polysilicon, the polysilicon reacts with oxygen to form silicon oxide in subsequent thermal oxidation processes including the process for forming the gate oxide layer 70. It is well known that when a silicon oxide layer is formed by oxidizing silicon, the volume thereof increases. Hence, oxidation of the lower isolation pattern 50 made of polysilicon causes a stress to be applied to the substrate 10. Due to this stress, the substrate 10 may suffer from lattice damage 80, thereby degrading the characteristics of the semiconductor devices made in the substrate.
Alternatively, if the lower isolation pattern 50 is made of SOG, which is a liquid-phase material containing siloxanes or silicates mixed with solvent, an annealing step for evaporating the solvent is needed in order to use the SOG as an insulator. During this annealing step and during other subsequent high temperature processing steps, the carbon-containing materials may diffuse into the substrate 10. If the carbon-containing materials diffuse into the substrate, electrical characteristics of a semiconductor device become unstable.
The present invention provides a novel trench device isolation structure and a method of forming the same. The novel trench device isolation structure suppresses the oxidation and the consequent expansion of a lower isolation pattern that otherwise may create stress in the substrate. The novel trench device isolation structure also prevents diffusion of impurities from the lower isolation pattern into the substrate.
According to an aspect of an embodiment of the present invention, a method of forming a trench device isolation structure includes forming a trench in a predetermined area of a semiconductor substrate to define an active region; forming a lower isolation pattern having a top surface at a lower level than a top surface of the semiconductor substrate; and forming an upper liner pattern to cover an upper portion of an inner sidewall of the trench and the top surface of the lower isolation pattern and an upper isolation pattern to fill an area surrounded by the upper liner pattern. According to a feature of an embodiment of the present invention, a thermal oxide layer may be formed on an inner sidewall of the trench following the formation of the trench. This method may further include forming a lower liner on an entire surface of the semiconductor substrate including the trench following the formation of the trench or following the formation of the thermal oxide layer.
According to an embodiment of the present invention, forming the lower isolation pattern in the method of forming a trench device isolation structure may further include forming a lower device isolation layer on the entire surface of the semiconductor substrate including the trench to fill the trench; and etching the lower device isolation layer until a top surface of the lower device isolation layer is at a level lower than a top surface of the active region in the trench.
According to another aspect of an embodiment of the present invention, forming the upper liner pattern and the upper isolation pattern in the method of forming a trench isolation structure may include forming an upper liner on an entire surface of a semiconductor substrate, including the lower isolation pattern; forming an upper device isolation layer on the upper liner; and sequentially etching the upper device isolation layer and the upper liner to expose the top surface of the semiconductor substrate. In yet another aspect of an embodiment of the present invention, a low pressure chemical vapor deposition (LPCVD) oxide layer is formed on the upper liner prior to the formation of the upper device isolation layer, and a tetra-ethyl-ortho-silicate (TEOS) layer is formed on the upper device isolation layer.
According to a feature of an embodiment of the present invention, forming a trench in the method of forming a trench isolation structure may include forming a pad oxide layer, a polish-stop layer, and a hard mask layer sequentially on the semiconductor substrate; patterning the hard mask layer, the polish-stop layer, and the pad oxide layer sequentially to form a trench mask pattern; and anisotropically etching the substrate. According to yet another feature of an embodiment of the present invention, the trench mask pattern includes an anti-reflective film pattern formed on the hard mask layer pattern. According to still another feature of an embodiment of the present invention, the anti-reflective film pattern and the hard mask layer pattern are removed during the substrate etching; and the polish-stop layer pattern and the pad oxide layer pattern are isotropically etched.
In accordance with some of the features of an embodiment of the present invention, the upper liner pattern and the lower liner pattern are preferably made of a material having a good oxygen and other impurities diffusion blocking property, such as silicon nitride; the lower isolation pattern is preferably made of a material having a good filling property, such as polysilicon, silicon-on-glass (SOG), boro-phospho-silicate glass (BPSG), phospho-silicate glass (PSG), boro-silicate glass (BSG), and tetra-ethyl-ortho-silicate (TEOS); the upper isolation pattern is preferably made of an insulator that is stable during a thermal process, such as high density plasma (HDP) oxide or undoped silicate glass (USG).
According to yet still another embodiment of the present invention, a device isolation structure includes a trench formed in a predetermined area of a semiconductor substrate to define an active region; a lower isolation pattern having a top surface that is at a lower level than a top surface of the active region, the lower isolation pattern being formed in the trench; and an upper isolation pattern formed on the lower isolation pattern, wherein a sidewall and a bottom of the upper isolation pattern are surrounded by the upper liner pattern. The above isolation structure may further include a thermal oxide layer covering the inner sidewall of the trench.
In one of the aspects of an embodiment of the present invention, the device isolation structure includes a lower liner pattern covering an inner wall of the trench. In another aspect of an embodiment of the present invention, a thermal oxide layer intervenes between the lower liner pattern and the semiconductor substrate.
These and other features and advantages of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.